1. Field of the Invention
This invention generally relates to complementary metal/oxide/semiconductor (CMOS) imaging sensors and, more particularly, to an imager pixel transistor set for reading signals from triple-junction photodiodes formed in a bulk silicon substrate.
2. Description of the Related Art
FIG. 1 is a schematic diagram depicting an active pixel sensor (APS) imager cell made with n-channel MOS (NMOS) transistors (prior art). The APS cell includes a reset transistor, source follower transistor, select transistor, and a photodiode. All three transistors in the APS cell are NMOS. The drain and source terminals of the reset transistor are respectively coupled to a reference supply (VRef) and a cathode (node 1) of photodiode, whose anode is coupled to a ground or fixed reference voltage (VSS). The source terminal of reset transistor drives the gate terminal of source follower transistor, whose drain and source terminals are coupled, respectively, to a power supply (VDD) and drain terminal of the select transistor. The reference supply (VRef) may be, but need not be, equal to the power supply (VDD). During operation, a high reset voltage (VReset) is initially provided at the reset transistor to pull node 1 up to a dark reference voltage (VDark). If the active reset voltage is high enough to keep reset transistor in the linear region, the dark reference voltage VDark equals VRef. When the reset voltage is turned off, the charge trapped at photodiode cathode (i.e., node 1) maintains a high voltage there. When the APS cell is exposed to light, the photodiode discharges node 1, to bring the voltage at node 1 towards the ground reference voltage. The voltage at node 1 can be read by turning on the select transistor, which is done by applying a selection voltage to the gate terminal of the select transistor, and sensing the output voltage VOut. For an undischarged pixel, voltage VOut is given by:Vout=VDark−Vnoise−VTNwhere VDark is the dark reference voltage at node 1, Vnoise represents a reset noise, and VTN is the threshold voltage for source follower transistor.
FIG. 2A is a schematic diagram depicting a bulk silicon (Si) six-transistor (6T) stacked junction imager cell (prior art). The 6T cell includes the 3T cell of FIG. 1, plus additional transfer transistors.
FIG. 2B is a partial cross-sectional view of a stacked set of photodiodes formed in a Si-on-insulator (SOI) substrate (prior art). The photodiode set 200 includes three stacked photodiodes 202, 204, and 206. Note, none of the photodiodes share a junction. That is, the p-doped and n-doped areas of the three diodes are distinct and separate. The photodiode set is controlled by a transistor set, such as the set shown in FIG. 2A or FIG. 3, which is represented in this figure by transistor 208.
FIG. 3 is a schematic diagram depicting a bulk Si nine-transistor (9T) stacked junction imager cell (prior art). The 9T cell includes three of the 3T cells of FIG. 1. Stacked photodetectors are used for color imaging, one diode for each of the red (R), green (G), and blue (B) colors. A stacked RGB photodiode can directly measure red, green, and blue signals by efficiently stacking three photodiodes on top of one another using a triple-well CMOS process wherein the blue, green, and red sensitive pn junctions are disposed at different depths beneath the surface of a semiconductor substrate upon which the imager is formed (see FIG. 2B). This technology increases the sampling density, improves sharpness, and eliminates the color aliasing artifacts. Further, this technology does not require color filters.
FIGS. 4A and 4B depict a silicon-on-insulator (SOI) version of a multi-junction filterless color imager (prior art). The blue diode D1 is fabricated at SOI top silicon film. The green diode is the P+N diode and the red diode are the N−P-substrate diode. The structure is very simple. The APS circuit is shown in FIG. 4B where the red diode output is read at M5. The source follower, M6, reads a differential signal responsive to both the red and green photodiode. There is no direct green diode read out capability. The blue diode is fabricated SOI top Si layer and the APS circuit of the blue diode is a conventional unit as is shown in FIG. 1.
FIGS. 18A and 18B are drawings depicting a five-junction photodiode imager and corresponding transistor set for reading the diode signals (prior art). In U.S. Pat. Nos. 6,476,372 and 6,960,757, Merrill et al. disclose a filterless color CMOS imager cell having an n1/p1/n2/p2/n3/p-substrate structure. The pixel consists of five (5) junctions. All the p-type layers are grounded. The n1/p1 interface forms a junction for blue diode. The green diode is formed by the parallel combination of the n2/p1 and n2/p2 junctions. The red diode is formed by the parallel combination of the n3/p2 and n3-p-substrate junctions. Since n2/p1 and n2/p2 diodes have a common cathode and the anodes are all grounded, the voltage of the n2/p1 junction is equal to that of the voltage of the n2/p2 junction. Similarly, the voltage of the n3/p2 junction is equal to that of n3/p-substrate. Therefore, the photovoltaic voltage of green diode is about the average of the photovoltaic voltage for the n2/p1 and n2/p2 junctions, but it is not the sum of the n2/p1 and n2/p2 junctions. Two photodiodes in parallel do not generate two times the photovoltaic voltage.
The photon absorption spectra are mainly dependant upon the depth of silicon. The number of electron-hole pairs generated by incident light increases with the width of the depletion layer. The depth of the junctions for each diode color is very much fixed. As a result, the width of the depletion regions of the red and green diode junctions is much narrower than that of photodiode with a single depletion layer. The green diode and the red diode output voltages are much smaller than that of a single diode, since the width of each of the two diodes cannot be made larger than a single depletion width in any given junction depth. In addition, the area of each junction has to be properly increased with the depth of the junction in order to avoid shorting between adjacent junctions at the surface. As a result, the solar cell pixel filling factor decreases and the pixel size increases.
Some of the above-mentioned problems can be addressed using a silicon-on-insulator (SOI) structure. Although the SOI structure is able to reduce the number of junctions required, increase the filling factor, and reduce the pixel size, the wafer bonding process is not a common process in a conventional CMOS wafer fabrication facility.
Therefore, it is desirable to have a filterless triple-junction CMOS color imager that is fabricated in bulk silicon, without using a SOI process.
It would be advantageous if the triple-junction photodiode imager could be enabled with an imager sensing transistor set to independently read the output of each photodiode.